Display device and driving method thereof

ABSTRACT

An object is to reduce residual images and power consumption in a liquid crystal display device. The liquid crystal display device capable of inputting an image signal to a pixel portion selectively is provided. It is possible for the liquid crystal display device to input the image signal only to a region in which a fast-moving image is displayed. Therefore, residual images in displaying a moving image can be reduced. Further, in the liquid crystal display device, it is acceptable that the image signal is not input to a region in which a slow-moving image is displayed; accordingly, power consumption can be reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to liquid crystal display devices. Inparticular, the present invention relates to liquid crystal displaydevices capable of frame rate driving. In addition, the presentinvention relates to a driving method of the liquid crystal displaydevices.

2. Description of the Related Art

Display devices such as liquid crystal display devices form images(still images) based on image signals input from the outside andsequentially display the images, thereby displaying moving images.

Note that the moving image is formed of many still images. That is,strictly speaking, the moving image is not a continuous image.Accordingly, when fast moving images are displayed, residual images arelikely to be generated in display. Particularly in liquid crystaldisplay devices, each pixel maintains display from when an image signalis input to the pixel to when the next image signal is input to thepixel; therefore, residual images tend to be apparent.

In Patent Document 1, a technique to reduce the above-described residualimages (referred to as “double-frame rate driving” in general) isdisclosed. Specifically, in Patent Document 1, the following techniqueis disclosed: an image for interpolation is formed between two imagesdisplayed sequentially, and the image is inserted between two imagesdisplayed sequentially, so that residual images are reduced.

REFERENCE

-   [Patent Document 1] Japanese Published Patent Application No.    H04-302289

SUMMARY OF THE INVENTION

In many liquid crystal display devices, a capacitor is provided for eachpixel so that voltage applied to liquid crystal elements can be held andinversion driving is performed to suppress deterioration of the liquidcrystal elements. That is, power consumption is largely changed inaccordance with the number of image signals input to each pixel.Meanwhile, it can be said that the above technique is a technique forincreasing the number of image signals input to each pixel included in aliquid crystal display device per unit time. Therefore, in the liquidcrystal display device for which the technique is used, an increase inpower consumption is inevitable.

In a view of the above problems, it is an object of one embodiment ofthe present invention to provide liquid crystal display devices in whichreduction both in residual images and in power consumption can berealized.

The above problems can be solved by inputting an image signal forforming an interpolation image to a pixel portion selectively.

That is, one embodiment of the present invention is a liquid crystaldisplay device in which a pixel portion is divided into a plurality ofregions and whether an image signal is input or not is selecteddepending on a region of the plurality of regions.

As a specific example of the above liquid crystal display device, aliquid crystal display device described below can be given.

That is, one embodiment of the present invention is a liquid crystaldisplay device including a processor which compares a first image and asecond image formed in accordance with image signals input from theoutside and generates an image signal for forming a third image forbeing interpolated between the first image and the second image; a gatedriver and a source driver whose operation is controlled by an outputsignal of the processor; and a pixel portion where display is performedby output signals of the gate driver and the source driver. The pixelportion is divided into a plurality of regions and whether the imagesignal for forming the third image is input is selected depending on aregion of the plurality of regions.

Further, in a liquid crystal display device according to one embodimentof the present invention, the number of interpolation images is notlimited to one.

That is, one embodiment of the present invention also includes a liquidcrystal display device including a processor which compares a firstimage and a second image formed in accordance with image signals inputfrom the outside and generates an image signal for forming a third imageto an n-th image (n is a natural number of 4 or more) for beinginterpolated between the first image and the second image; a gate driverand a source driver whose operation is controlled by an output signal ofthe processor; and a pixel portion where display is performed by outputsignals of the gate driver and the source driver. The pixel portion isdivided into a plurality of regions and whether the image signals forforming the third image to the n-th image are input is selecteddepending on a region of the plurality of regions.

Furthermore, a liquid crystal display device according to one embodimentof the present invention can selectively input an image signal inputfrom the outside to a pixel portion.

That is, one embodiment of the present invention also includes a liquidcrystal display device including a processor which compares a firstimage to an n-th image (n is a natural number of 2 or more) formed inaccordance with image signals input from the outside; a gate driver anda source driver whose operation is controlled by an output signal of theprocessor; and a pixel portion where display is performed by outputsignals of the gate driver and the source driver. The pixel portion isdivided into a plurality of regions and whether the image signals forforming the first image to the n-th image are input is selecteddepending on a region of the plurality of regions.

Further, a liquid crystal display device according to one embodiment ofthe present invention can selectively input an image signal for formingan interpolation image to a pixel portion and selectively input an imagesignal input from the outside to a pixel portion, concurrently.

That is, one embodiment of the present invention also includes a liquidcrystal display device including a processor which compares a firstimage to an n-th image (n is a natural number of 2 or more) formed inaccordance with image signals input from the outside, compares a k-thimage (k is a natural number of 1 or more and less than n) and a(k+1)-th image, and generates image signals for forming an (n+1)-thimage to an m-th image (m is a natural number of (n+2) or more) forbeing interpolated between the k-th image and the (k+1)-th image; a gatedriver and a source driver whose operation is controlled by an outputsignal of the processor; and a pixel portion where display is performedby output signals of the gate driver and the source driver. The pixelportion is divided into a plurality of regions and whether the imagesignals for forming the first image to the m-th image are input isselected in accordance with a region of the plurality of regions.

According to one embodiment of the present invention, an image signalcan selectively be input to a pixel portion. That is, the one embodimentof the present invention can input the image signal only to a region inwhich a fast-moving image is displayed. Therefore, residual images indisplaying a moving image can be reduced. Further, it is possible thatthe image signal is not input to a region in which a slow-moving imageis displayed. Accordingly, power consumption can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a liquid crystal display device according toEmbodiment 1.

FIGS. 2A and 2B illustrate a liquid crystal display device according toEmbodiment 1.

FIGS. 3A and 3B illustrate a liquid crystal display device according toEmbodiment 1.

FIG. 4 illustrates a liquid crystal display device according toEmbodiment 1.

FIGS. 5A to 5D illustrate a liquid crystal display device according toEmbodiment 1.

FIG. 6 illustrates a liquid crystal display device according toEmbodiment 1.

FIGS. 7A and 7B illustrate a liquid crystal display device according toEmbodiment 2.

FIG. 8 is a longitudinal sectional view of an inverted-staggered thinfilm transistor including an oxide semiconductor.

FIGS. 9A and 9B are energy band diagrams (schematic diagrams)corresponding to a cross section taken along line A-A′ in FIG. 8.

FIG. 10A is a diagram illustrating a state where a positive potential(+VG) is applied to a gate electrode layer (GE1), and FIG. 10B is adiagram illustrating a state where a negative potential (−VG) is appliedto the gate electrode layer (GE1).

FIG. 11 illustrates a relation between the vacuum level and the workfunction of a metal (φM) and a relation between the vacuum level and theelectron affinity of an oxide semiconductor (χ).

FIGS. 12A to 12D illustrate manufacturing steps of a thin filmtransistor.

FIGS. 13A to 13D each illustrate a liquid crystal display deviceaccording to Embodiment 2.

FIGS. 14A to 14C each illustrate a liquid crystal display deviceaccording to Embodiment 3.

FIGS. 15A and 15B each illustrate a liquid crystal display deviceaccording to Embodiment 3.

FIGS. 16A to 16C illustrate a liquid crystal display device according toEmbodiment 3.

FIG. 17 illustrates a liquid crystal display device according toEmbodiment 3.

FIGS. 18A to 18F each illustrate an electronic device according toEmbodiment 4.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that thepresent invention is not limited to the description below, and it iseasily understood by those skilled in the art that a variety of changesand modifications can be made without departing from the spirit andscope of the present invention. Therefore, the present invention shouldnot be limited to the descriptions of the embodiments below.

Note that since a source terminal and a drain terminal of a transistorchange depending on the structure, the operating condition, or the likeof the transistor, it is difficult to define which is a source terminalor a drain terminal. Therefore, one of a source terminal and a drainterminal is referred to as a first terminal and the other is referred toas a second terminal for distinction in this specification.

Note that the size, the thickness of a layer, or a region of eachstructure illustrated in drawings or the like in embodiments isexaggerated for simplicity in some cases. Therefore, the actual scale isnot limited to such a scale. Further, in this specification, ordinalnumbers such as “first”, “second”, and “third” are used in order toavoid confusion among components, and the terms do not limit thecomponents numerically.

Embodiment 1

In Embodiment 1, an example of an active matrix liquid crystal displaydevice is described. Specifically, an active matrix liquid crystaldisplay device which can select whether double-frame rate driving isperformed on a region of a plurality of regions included in a pixelportion is described with reference to FIGS. 1A and 1B, FIGS. 2A and 2B,FIGS. 3A and 3B, FIG. 4, FIGS. 5A to 5D, and FIG. 6.

A liquid crystal display device in Embodiment 1 can store image datawhich is formed on the basis of an image signal input from the outsidefor a certain period. In addition, the liquid crystal display device ofEmbodiment 1 can store data of a plurality of images and can detect amotion vector by comparison between two images displayed sequentially.At this time, an interpolation image of two images displayedsequentially is formed on the basis of the motion vector. Note that thenumber of the interpolation image is not limited to one. It is possibleto change the number of the images depending on the magnitude of themotion vector. Further, an image signal for displaying the interpolationimage can be selectively input to each region of a pixel portiondepending on the magnitude of the motion vector.

A structure example and an operation example of the liquid crystaldisplay device of Embodiment 1 will be described below with reference toFIGS. 1A and 1B. A liquid crystal display device in FIG. 1A includes aprocessor 10 to which an image signal is input from the outside, a pixelportion 13 which includes a plurality of pixels arranged in matrix, anda gate driver 11 and a source driver 12 operation of which is controlledby an output signal from the processor 10. Note that the gate driver 11controls the plurality of pixels so that an image signal can be inputthereto every row. The source driver 12 outputs an image signal to theplurality of pixels.

<Original DATA>

Here, an image signal for forming an image a (an image in which a squareand a circle are depicted in an upper-left region and a lower-centerregion, respectively) in FIG. 1B, and an image signal for forming animage b (an image in which a square and a circle are depicted in anupper-right region and a lower-center region, respectively) are inputfrom the outside to the processor 10. Note that the positions of thecircles in the images a and b are the same.

<Production DATA>

The processor 10 detects a motion vector by comparison between theimages a and b. Image signals for forming an image c, an image d, and animage e are generated. The images c to e are interpolation images of theimages a and b. That is, a square in the image c is moved from theposition of the square in the image a toward that in the image b by onefourth of the distance between the positions, the square in the image dis moved to the middle between the position of the square in the image aand that in the image b, and the square in the image e is moved from theposition of the square in the image a toward that in the image b bythree fourth of the distance between the positions. Note that thepositions of circles in the images a to e are the same.

<Input DATA>

The image a, the images c to e, and the image b are sequentiallydisplayed in the pixel portion 13 after the image signals for formingthe images c to e are generated. Specifically, image signals fordisplaying the image a, the images c to e, and the image b are inputfrom the source driver 12 to a plurality of pixels included in the pixelportion 13. Note that the image signals for displaying the images c to eare input to a pixel group (pixels 141, 142, 143, 144, and the like)included in a region 14 but not to a pixel group (pixels 151, 152, 153,154, and the like) included in a region 15 (see FIG. 1A). That is, asillustrated in FIG. 1B, an image f, an image g, and an image h areinterpolated between the images a and b. Note that the image fcorresponds to the upper region of the image c, the image g correspondsto the upper region of the image d, and the image h corresponds to theupper region of the image e. Further, when image signals of the images fto h are input, an image signal is not input to the lower region of thepixel portion 13 and an image in the lower region of the image a isheld. Furthermore, in the liquid crystal display device of Embodiment 1,the processor 10 determines a pixel group in a region of the pixelportion 13, to which an image signal for forming an interpolation imageis input. Specifically, the region is determined by the magnitude of themotion vector which is detected by comparison between the images a andb.

The liquid crystal display device of Embodiment 1 generates an imagesignal (Production DATA) for forming an interpolation image based on animage signal (Original DATA) input from the outside. Further, the imagesignal (Production DATA) for forming an interpolation image is input toa pixel group included in a certain region, not to all of the pixelsincluded in the pixel portion. The region is the region in which themotion vector detected by the image signal (Original DATA) input fromthe outside is large; that is, the region in which a residual imagebecomes apparent. In other words, the image signal (Production DATA) forforming an interpolation image is not input to a pixel group included ina region in which a residual image is not apparent. Therefore, residualimages can be reduced in displaying moving images and the increase inpower consumption can be suppressed.

Specific Example

A specific example of the above liquid crystal display device will bedescribed below with reference to FIGS. 2A and 2B. FIG. 2A illustrates astructure of the gate driver 11 in more detail. The gate driver 11illustrated in FIG. 2A includes a shift register 20 to which a signal isinput from the processor 10, and an output control circuit 21 to which asignal is input from the processor 10 and the shift register 20. Notethat the processor 10 outputs a start pulse signal (SP), a clock signal(CK), and the like to the shift register 20, and outputs an outputcontrol signal (CS) or the like to the output control circuit 21.

The shift register 20 outputs a signal which controls switching ofswitches included in a plurality of pixels arranged in matrix andincluded in the pixel portion 13. Specifically, the shift register 20includes a plurality of flip-flops connected in series (not shown). Inthe shift register 20, an output signal of a flip-flop is sequentiallyshifted to the next flip-flop and output to the output control circuit21.

The output control circuit 21 selects whether the inputted signal fromthe shift register 20 is output to the pixel portion 13 or not.Specifically, as illustrated in FIG. 2B, the output control circuit 21includes a plurality of AND gates 22, 23, and 24. A first input terminalof each AND gate is electrically connected to a wiring (hereinafter,also referred to as a control signal line) supplying the control signal(CS) output from the processor 10. A second input terminal of the ANDgate is electrically connected to a wiring supplying an output signal ofone of the flip-flops included in the shift register 20. That is, afirst input terminal of the AND gate 22 is electrically connected to thecontrol signal line and a second input terminal of the AND gate 22 iselectrically connected to a wiring supplying an output signal (FF1out)of a flip-flop of the first stage included in the shift register 20.Similarly, first input terminals of the AND gate 23 and the AND gate 24are electrically connected to the control signal line and secondterminal of the AND gate 23 and second terminal of the AND gate 24 areelectrically connected to a wiring supplying an output signal (FF2out)of a flip-flop of the second stage included in the shift register 20 anda wiring supplying an output signal (FF3out) of a flip-flop of the thirdstage included in the shift register 20, respectively. Further, anoutput signal of the AND gate 22 is input to the plurality of pixelswhich are arranged in the first row among a plurality of pixels arrangedin matrix and included in the pixel portion 13. Similarly, an outputsignal of the AND gate 23 is input to a plurality of pixels arranged inthe second row, and an output signal of the AND gate 24 is input to aplurality of pixels arranged in the third row.

In a liquid crystal display device including the gate driver 11 with theabove structure, the control signal (CS) output from the processor 10makes it possible to select whether an image signal is input or not to aplurality of pixels which are arranged in matrix and included in thepixel portion 13 depending on a row. Specifically, the following isacceptable: the control signal (CS) is synchronized with an outputsignal of a flip-flop when an image signal is input to a plurality ofpixels arranged in a specific row, and the control signal (CS) is notsynchronized with an output signal of a flip-flop when an image signalis not input thereto. Note that it is not necessary that the controlsignal (CS) is completely synchronized with an output signal of aflip-flop even in the case where an image signal is input to a pluralityof pixels arranged in a specific row. For example, the pulse width ofthe control signal (CS) can be smaller than that of an output signal ofthe flip-flop, which reduces malfunctions such as the case where animage signal is input to a pixel except for a pixel to which the imagesignal is to be input. In addition, it is also acceptable that the aboveliquid crystal display device has a structure in which an output signalof the output control circuit 21 is input to the pixel portion 13through a buffer circuit and/or the like.

Further, in the above liquid crystal display device, local dimming ispreferably performed in accordance with an image signal for forming aninterpolation image. Note that local dimming means the process forcontrolling a backlight included in the liquid crystal display devicelocally. Local dimming enables improvement in the contrast of a movingimage displayed by the liquid crystal display device.

Moreover, in the above liquid crystal display device, backlight scanningis preferably performed. Note that backlight scanning means the processfor turning off the backlight for a split second in switching imagesdisplayed by the liquid crystal display device. Backlight scanningenables further reduction of residual images in displaying a movingimage of the liquid crystal display device. Note that backlight scanningcan be performed on the entire pixel portion or part of the pixelportion. For example, as illustrated in FIG. 1B, when an image signalfor interpolation is input only to the upper region (the region 14) ofthe pixel portion 13, backlight scanning or the like can be performedonly on the upper region before the image signal is input.

Further, the above liquid crystal display device can have a structure inwhich the source driver 12 is deactivated by stopping supply of a signalfrom the processor 10 to the source driver 12 or a structure in whichwhether an image signal is input from the source driver 12 to the pixelportion 13 or not is selected.

A specific example of the latter structure will be described withreference to FIGS. 3A and 3B. FIG. 3A illustrates a structure of thesource driver 12 in more detail. The source driver 12 illustrated inFIG. 3 includes a shift register 30 to which a signal is input from theprocessor 10, an output control circuit 31 to which a signal is inputfrom the processor 10 and the shift register 30, and a sampling circuit32 to which an image signal from the processor 10 and a signal from theoutput control circuit 31 are input. Note that the processor 10 outputsthe start pulse signal (SP), the clock signal (CK), and the like to theshift register 30, outputs the output control signal (CS) or the like tothe output control circuit 31, and outputs an image signal (DATA) or thelike to the sampling circuit 32.

The shift register 30 outputs a signal for controlling the samplingcircuit 32. Specifically, the shift register 30 includes a plurality offlip-flops connected in series (not shown). In the shift register 30, anoutput signal of a flip-flop is sequentially shifted to the nextflip-flop and output to the output control circuit 31.

The output control circuit 31 selects whether the inputted signal fromthe shift register 30 is output to the sampling circuit 32 or not.Specifically, as illustrated in FIG. 3B, the output control circuit 31includes a plurality of AND gates 33, 34, and 35. A first input terminalof the AND gate is electrically connected to a wiring (hereinafter, alsoreferred to as a source driver control signal line) which supplies acontrol signal for the source driver (CS(SD)) output from the processor10. A second input terminal of each AND gate is electrically connectedto a wiring supplying an output signal of one of the flip-flops includedin the shift register 30. That is, a first input terminal of the ANDgate 33 is electrically connected to the source driver control signalline and a second input terminal of the AND gate 33 is electricallyconnected to a wiring supplying an output signal (FF1out(SD)) of aflip-flop of the first stage included in the shift register 30.Similarly, first input terminals of the AND gate 34 and the AND gate 35are electrically connected to the source driver control signal line andsecond terminals of the AND gate 34 and the AND gate 35 are electricallyconnected to a wiring supplying an output signal (FF2out(SD)) of aflip-flop of the second stage included in the shift register 30 or awiring supplying an output signal (FF3out(SD)) of a flip-flop of thethird stage included in the shift register 30.

The sampling circuit 32 includes a plurality of analog switches (notshown). In the plurality of analog switches, switching is controlled byan output signal of one of a plurality of flip-flops included in theshift register 30. In addition, each analog switch is electricallyconnected between a wiring supplying an image signal and the pixelportion. That is, switching of the plurality of analog switches issequentially performed, so that an image signal is input to theplurality of pixels included in the pixel portion.

As described above, by employing a structure in which an image signalinput from the source driver 12 to the pixel portion 13 is selected, aregion to be subjected to input of an image signal can be selected in atwo-dimensional area.

Modification Example

Note that the above liquid crystal display device is an example of theliquid crystal display device of Embodiment 1. The liquid crystaldisplay device of Embodiment 1 includes a liquid crystal display devicehaving a difference with the above liquid crystal display device.

For example, in the above liquid crystal display device, the pixelportion 13 is divided into two regions which are different in the numberof image signals input per unit time. However, the region can be dividedinto three or more regions.

Further, in the above liquid crystal display device, three images areinterpolated between two images formed by image signals input from theoutside, for example. However, the number of images for interpolation isnot limited to the particular number because the number of images may bedetermined in accordance with the motion vector detected from two imagessequentially displayed.

Furthermore, in the above liquid crystal display device, the pixelportion 13 is divided into a region to which an image signal generatedfor interpolation is input and a region to which the image signal is notinput, for example. However, the pixel portion 13 can additionallyinclude a region to which some of image signals generated forinterpolation are input. The above description will be explained indetail below with reference to FIG. 4 using the following case as anexample: an image signal for forming the image a is input from theoutside, and then, an image signal for forming an image i (an image inwhich a square and a circle are depicted in an upper-right region and alower-right region, respectively) is input. Note that the differencebetween the image i and the image b (see FIG. 1B) is the position of thecircle. The circle is depicted in the center-right region in the image bwhile the circle is depicted in the lower-right region in the image i.First, the image a and the image i are compared and a motion vector isdetected. Then, image signals are generated to form an image j, an imagek, and an image l in accordance with the motion vector. Note that theimages j to l are interpolation images of the images a and i. That is, asquare and a circle in the image j are moved from the position in theimage a to those in the image i by one fourth of the distance betweenthe positions of the square and the circle, the square and the circle inthe image k are moved toward the middle between the positions of thesquare and the circle in the image a and those in the image i, and thesquare and the circle in the image l are moved from the positions of thesquare and the circle in the image a toward those in the image i bythree fourth of the distance between the positions. Image signals forforming the images are input to the pixel portion. Note that the motionvector is large in the upper region of the pixel portion, whereas themotion vector is small in the lower region of the pixel portion. In thiscase, it is acceptable that image signals for generating the image j andthe image l are input to the upper region of the pixel portion and animage signal for generating the image k is input to an entire region ofthe pixel portion 13. That is, as illustrated in FIG. 4, an image m, theimage k, and an image n are interpolated between the images a and i.Note that the image m and the image n correspond to the upper region ofthe image j and the upper region of the image l, respectively.

Further, in the above liquid crystal display device, the image signalinput from the outside is just input to the pixel portion 13; however,the image signal can be selectively input thereto. For example, asillustrated in FIG. 5A, an image signal for forming the image a and animage signal for forming the image o can be just input from the outsideto the pixel portion 13 and an image signal for forming the image b canbe selectively input to the pixel portion 13 in the case where the imagesignal for forming the image a, the image signal for forming the imageb, and the image signal for forming the image a (an image in which asquare and a circle are depicted in an upper-left region and alower-center region, respectively) are sequentially input from theoutside. That is, as for the image b, the image signal for forming theimage b is not input to the pixel portion 13, but instead, an imagesignal for forming an image p can be input to the pixel portion 13. Notethat the image p corresponds to the upper region of the image b.Accordingly, power consumption can be further reduced.

Furthermore, as illustrated in FIG. 5B, it is acceptable that an imagesignal for forming an image q is not input to the pixel portion 13 inthe case where an image signal for forming the image a, the image signalfor forming the image q (an image in which a square and a circle aredepicted in the upper-left region and the lower-center region,respectively), and an image r (an image in which a square and a circleare depicted in the upper-left region and the lower-center region,respectively) are sequentially input from the outside.

Note that as illustrated in FIGS. 5C and 5D, as for a region or an imagein which the motion vector of a plurality of images formed in accordancewith image signals input from the outside is small, it is acceptablethat image signals are not input to part of or the whole of the pixelportion for the plurality of images.

In addition, in the above liquid crystal display device, an image signal(an image signal to the entire region of the pixel portion 13) forforming an interpolation image is generated and the image signal isselectively input to the pixel portion 13. However, a structure of theliquid crystal display device of Embodiment 1 is not limited to this;that is, it is also acceptable that an image signal for forming part ofan interpolation image is generated and the image signal is input to thepixel portion 13. For example, as illustrated in FIG. 6, image signalsfor forming an image s, an image t, and an image u which are images forbeing interpolated just the upper region (the region 14) of the pixelportion 13 can be generated and the image signals can be input to thepixel portion 13 when the image signals for forming the image a and theimage b are input from the outside.

Moreover, the above liquid crystal display device has a structure inwhich the gate driver 11 (or the source driver 12) includes the shiftregister and the output control circuit. However, the structure can bereplaced with a decoder. Thus, an image signal can be efficiently inputto a specific region of the pixel portion 13.

Note that this embodiment or part of this embodiment can be freelycombined with any of the other embodiments or part of any of the otherembodiments.

Embodiment 2

In Embodiment 2, an example of an active matrix liquid crystal displaydevice described in Embodiment 1 will be illustrated in more detail.Specifically, a structure of a pixel portion included in a liquidcrystal display device will be described with reference to FIGS. 7A and7B, FIG. 8, FIGS. 9A and 9B, FIGS. 10A and 10B, FIG. 11, FIGS. 12A to12D, and FIGS. 13A to 13D.

<Structure Example of Liquid Crystal Display Device>

A block diagram of a structure of a liquid crystal display device ofEmbodiment 2 is illustrated in FIG. 7A. The liquid crystal displaydevice illustrated in FIG. 7A includes a processor 70, a gate driver 71,a source driver 72, a pixel portion 73, a plurality of gate lines 74arranged in parallel, and a plurality of source lines 75 arranged inparallel. Note that the gate driver 71 is electrically connected to thepixel portion 73 through the plurality of gate lines 74, and the sourcedriver 72 is electrically connected to the pixel portion 73 through theplurality of source lines 75.

Further, the pixel portion 73 includes a plurality of pixels 76. Notethat the pixels 76 are arranged in matrix. In addition, each of theplurality of gate lines 74 is electrically connected to the plurality ofpixels 76 provided in each row, and each of the plurality of sourcelines 75 is electrically connected to the plurality of pixels 76provided in each column.

Note that as described in Embodiment 1, in the liquid crystal displaydevice of Embodiment 2, an image signal input from the outside and animage signal for interpolating images, which is formed using the imagesignal input from the outside, are input to a pixel through the sourceline 75. Thus, the source line 75 is preferably formed of alow-resistance conductive material in order not to cause a signal delay.For example, the source line 75 is preferably formed of a low-resistanceconductive material such as copper (Cu) or an alloy including copper(Cu) as a main structural element. Alternatively, the source line 75 hasa stacked-layer structure which includes a layer including copper (Cu)or an alloy including copper (Cu) as a main structural element, so thata signal delay can be suppressed. Similarly, the gate line 74 ispreferably formed to have a single layer formed of a low-resistanceconductive material such as copper (Cu) or an alloy including copper(Cu) as a main structural element or a stacked-layer structure includingthe layer.

A circuit diagram of the pixel 76 is illustrated in FIG. 7B. The pixel76 including a transistor 77 a gate terminal of which is electricallyconnected to the gate line 74 and a first terminal of which iselectrically connected to the source line 75, a capacitor 78 oneterminal of which is electrically connected to a second terminal of thetransistor 77 and the other terminal of which is electrically connectedto a wiring (also referred to as a common potential line) supplying acommon potential (Vcom), and a liquid crystal element 79 one terminal ofwhich is electrically connected to the second terminal of the transistor77 and the one terminal of the capacitor 78 and the other terminal ofwhich is electrically connected to the common potential line. Note thatin Embodiment 2, a ground potential, 0 V or the like is given as thecommon potential (Vcom).

<Structure Example of Transistor>

As the transistor 77 in Embodiment 2, a thin film transistor whosechannel formation region is formed using an oxide semiconductor isemployed. As the material of the oxide semiconductor, a four-componentmetal oxide such as an In—Sn—Ga—Zn—O-based metal oxide, athree-component metal oxide such as an In—Ga—Zn—O-based metal oxide, anIn—Sn—Zn—O-based metal oxide, an In—Al—Zn—O-based metal oxide, aSn—Ga—Zn—O-based metal oxide, an Al—Ga—Zn—O-based metal oxide, and aSn—Al—Zn—O-based metal oxide, or a two-component metal oxide such as anIn—Zn—O-based metal oxide, a Sn—Zn—O-based metal oxide, an Al—Zn—O-basedmetal oxide, a Zn—Mg—O-based metal oxide, a Sn—Mg—O-based metal oxide,an In—Mg—O-based metal oxide, an In—O-based metal oxide, a Sn—O-basedmetal oxide, and a Zn—O-based metal oxide can be used. In addition, anoxide semiconductor formed in such a manner that SiO₂ is added to theabove oxide semiconductor may be used.

As the oxide semiconductor film, a substance expressed by InMO₃(ZnO)_(m) (m>0) can be used. Here, M represents one or more metalelements selected from Ga, Al, Mn, and Co. For example, M can be Ga, Gaand Al, Ga and Mn, Ga and Co, or the like. An oxide semiconductor whosecomposition formula is represented by InMO₃ (ZnO)_(m) (m>0) where Ga isincluded as M is referred to as the In—Ga—Zn—O oxide semiconductordescribed above, and a thin film thereof is also referred to as anIn—Ga—Zn—O-based film.

FIG. 8 illustrates a longitudinal cross-sectional view of an invertedstaggered thin film transistor including a channel formation regionformed using an oxide semiconductor. An oxide semiconductor layer (OS)is provided over a gate electrode layer (GE1) with a gate insulatinglayer (GI) therebetween, and a source electrode layer (S) and a drainelectrode layer (D) are provided thereover.

FIGS. 9A and 9B are energy band diagrams (schematic diagrams) of thelayers of the thin film transistor in cross section taken along lineA-A′ in FIG. 8. FIG. 9A illustrates a case where the source and thedrain have voltages of the same potential (V_(D)=0 V). FIG. 9Billustrates a case where a positive potential is applied to the drain(V_(D)>0 V) whereas positive potential is not applied to the source.

FIGS. 10A and 10B are energy band diagrams (schematic diagrams) of thelayers of the thin film transistor in cross section taken along lineB-B′ in FIG. 8. FIG. 10A shows a state where a positive potential(+V_(G)) is applied to the gate electrode layer (GE1), that is, an onstate where carriers (electrons) flow between the source and the drain.FIG. 10B illustrates a state where a negative potential (−V_(G)) isapplied to the gate electrode layer (GE1), that is, an off state (astate where minority carriers do not flow).

FIG. 11 illustrates relation between the vacuum level and the workfunction of a metal (φ_(M)) and relation between the vacuum level andthe electron affinity of an oxide semiconductor (χ).

In FIG. 11, because metal is degenerated, the conduction band and theFermi level correspond to each other. On the other hand, a conventionaloxide semiconductor is generally n-type, and the Fermi level (E_(f)) inthat case is located closer to the conduction band and is away from theintrinsic Fermi level (Ei) that is located in the middle of the bandgap. Note that it is known that hydrogen is a donor in an oxidesemiconductor, which is known as a factor that causes the oxidesemiconductor to be an n-type oxide semiconductor.

In contrast, an oxide semiconductor described here is an intrinsic(i-type) or a substantially intrinsic oxide semiconductor which isobtained by removing hydrogen, which is an n-type impurity, from anoxide semiconductor and highly purifying the oxide semiconductor so thatimpurities that are not main components of the oxide semiconductor isprevented from being contained therein as much as possible. In otherwords, a highly purified i-type (intrinsic) semiconductor or asemiconductor close thereto is obtained not by adding an impurity but byremoving impurities such as hydrogen or water as much as possible. Thisenables the Fermi level (E_(f)) to be at the same level as the intrinsicFermi level (Ei).

It is said that the electron affinity (χ) of an oxide semiconductor is4.3 eV when the band gap (Eg) thereof is 3.15 eV. The work function oftitanium (Ti) used for forming the source electrode layer and the drainelectrode layer is substantially equal to the electron affinity (χ) ofthe oxide semiconductor. In that case, a Schottky barrier for electronsis not formed at an interface between the metal and the oxidesemiconductor.

In other words, in the case where the work function of metal (φM) andthe electron affinity (χ) of the oxide semiconductor are equal to eachother and the metal and the oxide semiconductor are in contact with eachother, an energy band diagram (a schematic diagram) as illustrated inFIG. 9A is obtained.

In FIG. 9B, a black circle () represents an electron. When a positivepotential is applied to the drain, the electron is injected into theoxide semiconductor layer over the barrier (h) and flows toward thedrain. In that case, the height of the barrier (h) changes depending onthe gate voltage and the drain voltage; in the case where positive drainvoltage is applied, the height of the barrier (h) is smaller than theheight of the barrier in FIG. 9A where no voltage is applied, that is, ½of the band gap (Eg).

In this case, as illustrated in FIG. 10A, the electron moves along thelowest part of the oxide semiconductor, which is energetically stable,at an interface between the gate insulating layer and thehighly-purified oxide semiconductor layer.

In FIG. 10B, when a negative potential (reverse bias) is applied to thegate electrode layer (GE1), the number of holes that are minoritycarriers is substantially zero; thus, the current value becomes a valueextremely close to zero.

For example, even when the thin film transistor has a channel width W of1×10⁴ μm and a channel length of 3 μm, an off current of 10⁻¹³ A orlower and a subthreshold value (S value) of 0.1 V/dec. (the thickness ofthe gate insulating film: 100 nm) can be obtained.

As described above, the oxide semiconductor is highly purified so thatimpurities that are not main components of the oxide semiconductor isprevented from being contained therein as much as possible, wherebyfavorable operation of the thin film transistor can be obtained.

The above oxide semiconductor is an oxide semiconductor which made to behighly purified and which is made to be electrically intrinsic asfollows: an impurity such as hydrogen, moisture, a hydroxy group, orhydride (also referred to as a hydrogen compound), which is a factor ofthe variation in electric characteristics, is intentionally eliminatedin order to suppress the variation, and oxygen which is a main componentof the oxide semiconductor and which is reduced by an impurityelimination process is supplied.

Accordingly, it is preferable that hydrogen be in the oxidesemiconductor as less as possible. It is preferable that hydrogenconcentration included in the oxide semiconductor be 1×10¹⁶/cm³ or lessand hydrogen included in the oxide semiconductor is reduced as much aspossible to be close to zero. Note that the concentration of hydrogen inthe oxide semiconductor may be measured by secondary ion massspectroscopy (SIMS).

Further, the high-purified oxide semiconductor has very few carriers(close to zero) and the carrier density is less than 1×10¹²/cm³,preferably less than 1×10¹¹/cm³. That is, the carrier density of theoxide semiconductor layer is reduced as much as possible to be extremelyclose to zero. Since there are extremely few carriers in the oxidesemiconductor layer, off-state current of a thin film transistor can below. It is preferable that off-state current be as small as possible. Inthe above thin film transistor, a current value per 1 μm of the channelwidth (W) can be 10 aA/μm (1×10⁻¹⁷/μm) or less, further, 1 aA/μm(1×10⁻¹⁸/μm) or less. In general, in a thin film transistor includingamorphous silicon, the current value is 1×10⁻¹³ A/μm or more. Further,since there is no pn junction and no hot carrier degradation, electriccharacteristics of the thin film transistor is not adversely affected.

The oxide semiconductor which is highly purified by drastically removinghydrogen contained in the oxide semiconductor layer as described aboveis used in a channel formation region of a thin film transistor, wherebya thin film transistor with an extremely small amount of off-statecurrent can be obtained. In addition, in circuit design, the oxidesemiconductor layer can be regarded as an insulator when the thin filmtransistor is in an off state. On the other hand, when the thin filmtransistor is in an on state, the current supply capability of the oxidesemiconductor layer is expected to be higher than the current supplycapability of a semiconductor layer formed of amorphous silicon.

When design or the like is performed, it is assumed that the off-statecurrent of a thin film transistor including low-temperature polysiliconis approximately ten thousand times as large as the off-state current ofa thin film transistor including an oxide semiconductor. Thus, thevoltage holding period of the thin film transistor including an oxidesemiconductor can be approximately ten thousand times as long as thevoltage holding period of the thin film transistor includinglow-temperature polysilicon. As an example, when a moving image isdisplayed at 60 frames per second, holding period of a thin filmtransistor including an oxide semiconductor for writing one signal canbe approximately 160 seconds, which is ten thousand times as long as theholding period of a thin film transistor including low-temperaturepolysilicon. In this manner, a still image can be displayed in a displayportion even by less frequent writing of image signals.

Long holding time allows frequency of supplying an image signal to apixel to be reduced. In particular, applying the above thin filmtransistor is very effective for the liquid crystal display device (seeFIGS. 5A to 5D) as described in Embodiment 1 in which an image signalinput from the outside to a pixel portion selectively. That is, in theliquid crystal display device, although a pixel to which an image signalis not input for a long time exists and the display quality of the pixelpossibly deteriorates, the above thin film transistor is used as aswitch for controlling input of an image signal to a pixel, whereby thedisplay of the pixel can be held for a long time.

Further, when the thin film transistor is used as a switch forcontrolling input of an image signal to a pixel, the size of a capacitorprovided in a pixel can be reduced. Thus, the aperture ration of thepixel can be high, an image signal can be input to the pixel at highspeed, for example.

<Manufacturing Process Example of Transistor>

One mode of a manufacturing method of the above thin film transistor isdescribed with reference to FIGS. 12A to 12D.

FIGS. 12A to 12D are figures illustrating an example of across-sectional structure of a thin film transistor. A thin filmtransistor 410 illustrated in FIGS. 12A to 12D is a kind of bottom-gatestructure called a channel-etched type and is also called an invertedstaggered thin film transistor.

Although a single-gate thin film transistor is illustrated in FIGS. 12Ato 12D, a multi-gate thin film transistor including a plurality ofchannel formation regions can be formed as needed.

A process for manufacturing the thin film transistor 410 over thesubstrate 400 is described below with reference to FIGS. 12A to 12D.

First, a conductive film is formed over the substrate 400 having aninsulating surface, and then, the gate electrode layer 411 is formedthrough a first photolithography step. Note that a resist mask used inthe process may be formed by an inkjet method. Formation of the resistmask by an inkjet method needs no photomask; thus, manufacturing costcan be reduced.

Although there is no particular limitation on a substrate which can beused as the substrate 400 having an insulating surface, it is necessarythat the substrate have at least enough heat resistance to withstandheat treatment to be performed later. For example, a glass substratemade of barium borosilicate glass, aluminoborosilicate glass, or thelike can be used. In the case where a glass substrate is used and thetemperature at which the heat treatment is to be performed later ishigh, a glass substrate whose strain point is 730° C. or more ispreferably used.

Further, an insulating film serving as a base film may be providedbetween the substrate 400 and the gate electrode layer 411. The basefilm has a function of preventing diffusion of an impurity element fromthe substrate 400, and can be formed with a single-layer structure or astacked-layer structure using one or more of a silicon nitride film, asilicon oxide film, a silicon nitride oxide film, and a siliconoxynitride film.

The gate electrode layer 411 can be formed to have a single-layer orstacked-layer structure using a metal material such as molybdenum,titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, orscandium, or an alloy material which contains any of these materials asits main component.

For example, as a two-layer structure of the gate electrode layer 411,the following structure is preferable: a structure in which a molybdenumlayer is stacked over an aluminum layer, a structure in which amolybdenum layer is stacked over a copper layer, a structure in which atitanium nitride layer or a tantalum nitride layer is stacked over acopper layer, or a structure in which a titanium nitride layer and amolybdenum layer are stacked. As a three-layer structure of the gateelectrode layer 411, a three-layer structure of a tungsten layer or atungsten nitride layer, a layer of an alloy of aluminum and silicon oran alloy of aluminum and titanium, and a titanium nitride layer or atitanium layer is preferable.

Then, a gate insulating layer 402 is formed over the gate electrodelayer 411.

The gate insulating layer 402 can be formed to have a single-layer orstacked-layer structure using one or more of a silicon oxide layer, asilicon nitride layer, a silicon oxynitride layer, a silicon nitrideoxide layer, an aluminum oxide layer, and the like by plasma CVD,sputtering, or the like. For example, a silicon oxynitride layer may beformed using a deposition gas containing silane (SiH₄), oxygen, andnitrogen by plasma CVD. Furthermore, a high-k material such as hafniumoxide (HfOx) or tantalum oxide (TaOx) can be used as the gate insulatinglayer. The thickness of the gate insulating layer 402 is 100 nm to 500nm, inclusive; in the case of a stacked layer, a first gate insulatinglayer having a thickness of 50 nm to 200 nm, inclusive, and a secondgate insulating layer having a thickness of 5 nm to 300 nm, inclusive,are stacked.

In this embodiment, a silicon oxynitride layer having a thickness of 100nm or less is formed by plasma CVD as the gate insulating layer 402.

Moreover, as the gate insulating layer 402, a silicon oxynitride filmmay be formed with a high density plasma apparatus. Here, a high-densityplasma apparatus refers to an apparatus which can realize a plasmadensity of 1×10¹¹/cm³ or more. For example, plasma is generated byapplying a microwave power of 3 kW to 6 kW inclusive so that theinsulating film is formed.

A silane gas (SiH₄), nitrous oxide (N₂O), and a rare gas are introducedinto a chamber as a source gas to generate high-density plasma at apressure of 10 Pa to 30 Pa, and the insulating film is formed over asubstrate having an insulating surface, such as a glass substrate. Afterthat, the supply of silane (SiH₄) is stopped, and plasma treatment maybe performed on a surface of the insulating film by introducing nitrousoxide (N₂O) and a rare gas without exposure to the air. The plasmatreatment performed on the surface of the insulating film by introducingnitrous oxide (N₂O) and a rare gas is performed at least after theinsulating film is formed. The insulating film formed through the aboveprocess procedure has small thickness and corresponds to an insulatingfilm whose reliability can be ensured even though it has a thicknessless than 100 nm, for example.

In forming the gate insulating layer 402, the flow ratio of silane(SiH₄) to nitrous oxide (N₂O) which are introduced into the chamber isin the range of 1:10 to 1:200. In addition, as a rare gas which isintroduced into the chamber, helium, argon, krypton, xenon, or the likecan be used. In particular, argon, which is inexpensive, is preferablyused.

In addition, since the insulating film formed by using the high-densityplasma apparatus can have a uniform thickness, the insulating film hasexcellent step coverage. Further, as for the insulating film formed byusing the high-density plasma apparatus, the thickness of a thin filmcan be controlled precisely.

The insulating film formed through the above process procedure isgreatly different from the insulating film formed using a conventionalparallel plate plasma CVD apparatus. The etching rate of the insulatingfilm formed through the above process procedure is lower than that ofthe insulating film formed using the conventional parallel plate plasmaCVD apparatus by 10% or more or 20% or more in the case where theetching rates with the same etchant are compared to each other. Thus, itcan be said that the insulating film formed using the high-densityplasma apparatus is a dense film.

The oxide semiconductor which becomes i-type or becomes substantiallyi-type (an oxide semiconductor which is highly purified) in a later stepis extremely sensitive to an interface state or an interface electriccharge; therefore, an interface with the gate insulating layer isimportant. Therefore, the gate insulating layer (GI) that is in contactwith the highly-purified oxide semiconductor needs to have higherquality. Therefore, high-density plasma CVD with use of microwaves (2.45GHz) is preferably employed since formation of a dense and high-qualityinsulating film having high withstand voltage can be formed. When thehighly-purified oxide semiconductor and the high-quality gate insulatinglayer are in close contact with each other, the interface state densitycan be reduced and favorable interface characteristics can be obtained.It is important that an insulating layer has a reduced interface statedensity with the oxide semiconductor and can form a favorable interfaceas well as having a favorable layer quality as a gate insulating layer.

Then, an oxide semiconductor film 430 is formed to have a thickness of 2nm to 200 nm inclusive over the gate insulating layer 402. Note thatbefore the oxide semiconductor film 430 is formed by sputtering, powderysubstances (also referred to as particles or dust) which are generatedat the time of the film formation and attached on a surface of the gateinsulating layer 402 are preferably removed by reverse sputtering inwhich an argon gas is introduced and plasma is generated. The reversesputtering refers to a method in which, without application of a voltageto a target side, an RF power supply is used for application of avoltage to a substrate side in an argon atmosphere to modify a surface.Note that instead of an argon atmosphere, a nitrogen atmosphere, ahelium atmosphere, an oxygen atmosphere, or the like may be used.

As the oxide semiconductor film 430, an In—Ga—Zn—O-based oxidesemiconductor film, an In—Sn—O-based oxide semiconductor film, anIn—Sn—Zn—O-based oxide semiconductor film, an In—Al—Zn—O-based oxidesemiconductor film, an Sn—Ga—Zn—O-based oxide semiconductor film, anAl—Ga—Zn—O-based oxide semiconductor film, an Sn—Al—Zn—O-based oxidesemiconductor film, an In—Zn—O-based oxide semiconductor film, anSn—Zn—O-based oxide semiconductor film, an Al—Zn—O-based oxidesemiconductor film, an In—O-based oxide semiconductor film, anSn—O-based oxide semiconductor film, or a Zn—O-based oxide semiconductorfilm is used. In Embodiment 2, the oxide semiconductor film 430 isformed by sputtering with the use of an In—Ga—Zn—O-based metal oxidetarget. A cross-sectional view at this stage is illustrated in FIG. 12A.Alternatively, the oxide semiconductor film 430 can be formed bysputtering in a rare gas (typically argon) atmosphere, an oxygenatmosphere, or a mixed atmosphere containing a rare gas (typicallyargon) and oxygen. When a sputtering method is employed, it ispreferable that deposition be performed using a target containing SiO₂of 2 percent by weight to 10 percent by weight and SiOx (x>0) whichinhibits crystallization be contained in the oxide semiconductor film430 so as to prevent crystallization at the time of the heat treatmentfor dehydration or dehydrogenation in a later step.

In this embodiment, film deposition is performed using a metal oxidetarget containing In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1 [mol],In:Ga:Zn=1:1:0.5 [atom]). The deposition condition is the following: thedistance between the substrate and the target is 100 mm, the pressure is0.2 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is amixed atmosphere of argon and oxygen (argon: oxygen=30 sccm:20 sccm andthe oxygen flow rate is 40%). Note that a pulse direct current (DC)power supply is preferably used because powder substances generated atthe time of deposition can be reduced and the film thickness can be madeto be uniform. The In—Ga—Zn—O-based film is formed to have a thicknessof 5 nm to 200 nm, inclusive. In this embodiment, as the oxidesemiconductor film, a 20-nm-thick In—Ga—Zn—O-based film is formed bysputtering with the use of an In—Ga—Zn—O-based oxide semiconductortarget. As the metal oxide target containing In, Ga, and Zn, a targethaving a composition ratio of In:Ga:Zn=1:1:1 (atom %) or a target havinga composition ratio of In:Ga:Zn=1:1:2 (atom %) can also be used.

Examples of sputtering include RF sputtering in which a high-frequencypower supply is used as a sputtering power supply, DC sputtering, andpulsed DC sputtering in which a bias is applied in a pulsed manner. RFsputtering is mainly used in the case where an insulating film isformed, and DC sputtering is mainly used in the case where a metal filmis formed.

In addition, there is also a multi-source sputtering apparatus in whicha plurality of targets of different materials can be set. With themulti-source sputtering apparatus, films of different materials can beformed to be stacked in the same chamber, or a film of plural kinds ofmaterials can be formed by electric discharge at the same time in thesame chamber.

In addition, there are a sputtering apparatus provided with a magnetsystem inside the chamber and used for a magnetron sputtering, and asputtering apparatus used for an ECR sputtering in which plasmagenerated with the use of microwaves is used without using glowdischarge.

Furthermore, as a deposition method by sputtering, there are alsoreactive sputtering in which a target substance and a sputtering gascomponent are chemically reacted with each other during deposition toform a thin compound film thereof, and a bias sputtering in whichvoltage is also applied to a substrate during deposition.

Then, the oxide semiconductor film 430 is processed into anisland-shaped oxide semiconductor layer through a secondphotolithography step. Note that a resist mask used in the process maybe formed by an inkjet method. Formation of the resist mask by an inkjetmethod needs no photomask; thus, manufacturing cost can be reduced.

Next, dehydration or dehydrogenation of the oxide semiconductor layersis performed. The temperature of first heat treatment for dehydration ordehydrogenation is 400° C. to 750° C. inclusive, preferably 400° C. ormore and lower than the strain point of the substrate. Here, thesubstrate is introduced into an electric furnace which is one of heattreatment apparatuses, heat treatment is performed on the oxidesemiconductor layer in a nitrogen atmosphere at 450° C. for one hour,and then, the oxide semiconductor layer is not exposed to the air sothat entry of water and hydrogen into the oxide semiconductor layer isprevented; thus, an oxide semiconductor layer 431 is obtained (see FIG.12B).

Note that a heat treatment apparatus is not limited to an electricalfurnace, and may include a device for heating an object by heatconduction or heat radiation from a heating element such as a resistanceheating element. For example, an RTA (rapid thermal anneal) apparatussuch as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamprapid thermal anneal) apparatus can be used. An LRTA apparatus is anapparatus for heating an object by radiation of light (anelectromagnetic wave) emitted from a lamp such as a halogen lamp, ametal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressuresodium lamp, or a high pressure mercury lamp. A GRTA apparatus is anapparatus for heat treatment using a high-temperature gas. As the gas,an inert gas which does not react with an object by heat treatment, suchas nitrogen or a rare gas such as argon is used.

For example, as the first heat treatment, GRTA by which the substrate ismoved into an inert gas heated to a high temperature as high as 650° C.to 700° C., heated for several minutes, and moved out of the inert gasheated to the high temperature may be performed. With GRTA,high-temperature heat treatment for a short period of time can beachieved.

Note that in the first heat treatment, it is preferable that water,hydrogen, and the like be not contained in the atmosphere of nitrogen ora rare gas such as helium, neon, or argon. Alternatively, it ispreferable that the purity of nitrogen or the rare gas such as helium,neon, or argon which is introduced into the heat treatment apparatus be6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, theimpurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

The first heat treatment of the oxide semiconductor layer may beperformed on the oxide semiconductor film 430 before being processedinto the island-shaped oxide semiconductor layer. In that case, afterthe first heat treatment, the substrate is extracted from the heattreatment apparatus, and then the second photolithography step isperformed.

The heat treatment for dehydration or dehydrogenation of the oxidesemiconductor layers may be performed at any of the following timings:after the oxide semiconductor layer is formed; after a source electrodelayer and a drain electrode layer are formed over the oxidesemiconductor layer; and after a protective insulating film is formedover the source electrode layer and the drain electrode layer.

Further, the step of forming the opening portion in the gate insulatinglayer 402 may be performed either before or after the oxidesemiconductor film 430 is subjected to dehydration or dehydrogenationtreatment.

Note that the etching of the oxide semiconductor film 430 is not limitedto wet etching and dry etching may also be used.

As the etching gas for dry etching, a gas including chlorine(chlorine-based gas such as chlorine (Cl₂), boron chloride (BCl₃),silicon chloride (SiCl₄), or carbon tetrachloride (CCl₄)) is preferablyused.

Alternatively, a gas containing fluorine (fluorine-based gas such ascarbon tetrafluoride (CF₄), sulfur fluoride (SF₆), nitrogen fluoride(NF₃), or trifluoromethane (CHF₃)); hydrogen bromide (HBr); oxygen (O₂);any of these gases to which a rare gas such as helium (He) or argon (Ar)is added; or the like can be used.

As the dry etching, parallel plate RIE (reactive ion etching) or ICP(inductively coupled plasma) etching can be performed. In order to etchthe films into desired shapes, the etching conditions (the amount ofelectric power applied to a coil-shaped electrode, the amount ofelectric power applied to an electrode on the substrate side, thetemperature of the electrode on the substrate side, or the like) isadjusted as appropriate.

As an etchant used for wet etching, a mixed solution of phosphoric acid,acetic acid, and nitric acid, or the like can be used. In addition,ITO07N (produced by KANTO CHEMICAL CO., INC.) may also be used.

The etchant after the wet etching is removed together with the etchedmaterials by cleaning. The waste liquid of the etchant including thematerial etched off may be purified and the included material may bereused. When a material such as indium included in the oxidesemiconductor layer is collected from the waste liquid after the etchingand reused, the resources can be efficiently used and the cost can bereduced.

The etching conditions (such as an etchant, etching time, ortemperature) are appropriately adjusted depending on the material sothat the material can be etched into a desired shape.

Next, a metal conductive film is formed over the gate insulating layer402 and the oxide semiconductor layer 431. The metal conductive film maybe formed by sputtering or vacuum evaporation. As a material of themetal conductive film, an element selected from aluminum (Al), chromium(Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), andtungsten (W), an alloy containing any of these elements as a component,an alloy containing any of these the elements in combination, or thelike can be given. Alternatively, one or more materials selected frommanganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), andyttrium (Y) may be used. Further, the metal conductive film may have asingle-layer structure or a stacked-layer structure of two or morelayers. For example, the following structures can be given: a singlelayer structure of an aluminum film including silicon, a single layerstructure of a copper film, or a film including copper as a maincomponent, a stacked-layer structure in which a titanium film is stackedover an aluminum film, a stacked-layer structure in which a copper filmis formed over a tantalum nitride film or a copper nitride film, and astacked-layer structure in which an aluminum film is stacked over atitanium film and a titanium film is stacked over the aluminum film.Alternatively, a film, an alloy film, or a nitride film which containsaluminum (Al) and one or a plurality of elements selected from titanium(Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr),neodymium (Nd), and scandium (Sc) may be used.

If heat treatment is performed after formation of the metal conductivefilm, it is preferable that the metal conductive film have enough heatresistance to withstand the heat treatment.

A third photolithography step is performed. A resist mask is formed overthe metal conductive film and etching is selectively performed, so thatthe source electrode layer 415 a and the drain electrode layer 415 b areformed. Then, the resist mask is removed (see FIG. 12C).

Note that materials and etching conditions are adjusted as appropriateso that the oxide semiconductor layer 431 is not removed by etching ofthe metal conductive film.

In Embodiment 2, a titanium film is used as the metal conductive film,an In—Ga—Zn—O based oxide is used for the oxide semiconductor layer 431,and an ammonia hydrogen peroxide solution (a mixture of ammonia, water,and a hydrogen peroxide solution) is used as an etchant.

Note that, in the third photolithography step, only a part of the oxidesemiconductor layer 431 is etched, whereby oxide semiconductor layerhaving groove (depressed portions) are formed in some cases.Alternatively, the resist mask used in the process may be formed by aninkjet method. Formation of the resist mask by an inkjet method needs nophotomask; thus, manufacturing cost can be reduced.

In order to reduce the number of photomasks used in a photolithographystep and reduce the number of photolithography steps, an etching stepmay be performed with the use of a resist mask formed using a multi-tonemask which is a light-exposure mask through which light is transmittedto have a plurality of intensities. Since a resist mask formed using amulti-tone mask has a plurality of thicknesses and can be furtherchanged in shape by performing ashing, the resist mask can be used in aplurality of etching steps to provide different patterns. Therefore, aresist mask corresponding to at least two kinds or more of differentpatterns can be formed by one multi-tone mask. Thus, the number oflight-exposure masks and the number of corresponding photolithographysteps can be reduced, whereby simplification of a process can berealized.

Then, plasma treatment with a gas such as nitrous oxide (N₂O), nitrogen(N₂), or argon (Ar) is performed. By this plasma treatment, absorbedwater and the like attached to an exposed surface of the oxidesemiconductor layer are removed. Plasma treatment may be performed usinga mixture gas of oxygen and argon as well.

After the plasma treatment, the oxide insulating layer 416 which servesas a protective insulating film and is in contact with part of the oxidesemiconductor layer is formed without exposure to the air.

The oxide insulating layer 416, which has a thickness of at least 1 nmor more, can be formed as appropriate by sputtering or the like, that isa method by which impurities such as water and hydrogen are not mixedinto the oxide insulating layer 416. When hydrogen is contained in theoxide insulating layer 416, entry of the hydrogen to the oxidesemiconductor layer is caused, thereby making a backchannel of the oxidesemiconductor layer 431 have a lower resistance (have n-typeconductivity) and forming parasitic channels. Therefore, it is importantthat a formation method in which hydrogen is not used is employed inorder to form the oxide insulating layer 416 containing as littlehydrogen as possible.

In Embodiment 2, a 200-nm-thick silicon oxide film is deposited as theoxide insulating layer 416 by sputtering. The substrate temperature infilm formation may be a room temperature or more and 300° C. or less andin Embodiment 2, is 100° C. Formation of a silicon oxide film bysputtering can be performed in a rare gas (typically, argon) atmosphere,an oxygen atmosphere, or an atmosphere of a rare gas (typically, argon)and oxygen. As a target, a silicon oxide target or a silicon target maybe used. For example, the silicon oxide film can be formed using asilicon target by sputtering in an atmosphere containing oxygen andnitrogen.

Next, second heat treatment is performed in an inert gas atmosphere oroxygen gas atmosphere (preferably at 200° C. to 400° C., inclusive,e.g., 250° C. to 350° C., inclusive). For example, the second heattreatment is performed in a nitrogen atmosphere at 250° C. for one hour.Through the second heat treatment, part of the oxide semiconductor layer(a channel formation region) is heated while being in contact with theoxide insulating layer 416. Thus, oxygen is supplied to part of theoxide semiconductor layer (a channel formation region).

Through the above steps, the oxide semiconductor layer is subjected tothe heat treatment for dehydration or dehydrogenation, and then, part ofthe oxide semiconductor layer (a channel formation region) isselectively made to be in an oxygen excess state. As a result, a channelformation region 413 overlapping with the gate electrode layer 411becomes i-type, and a source region 414 a overlapping with the sourceelectrode layer 415 a and a drain region 414 b overlapping with thedrain electrode layer 415 b are formed in a self-aligned manner. Thus,the thin film transistor 410 is formed.

When an oxide semiconductor containing an impurity is subjected to agate bias-temperature stress test (BT test) for 12 hours underconditions that the temperature is 85° C. and the voltage applied to thegate is 2×10⁶ V/cm, a bond between the impurity and a main component ofthe oxide semiconductor is cleaved by a high electric field (B: bias)and a high temperature (T: temperature), and a generated dangling bondinduces shift of threshold voltage (Vth). On the other hand, by removingimpurities in an oxide semiconductor as much as possible, especiallyhydrogen or water and performing the above high-density plasma CVD, sothat a dense and high-quality insulating film with high withstandvoltage and good interface characteristics between the insulating filmand an oxide semiconductor as described above can be obtained; thus, athin film transistor which is stable even in the BT test can beobtained.

Further, heat treatment may be performed at 100° C. to 200° C. inclusivefor from 1 hour to 30 hours inclusive in the air. In this embodiment,the heat treatment is performed at 150° C. for 10 hours. This heattreatment may be performed at a fixed heating temperature.Alternatively, the following change in the heating temperature may beconducted plural times repeatedly: the heating temperature is increasedfrom a room temperature to a temperature of 100° C. to 200° C. inclusiveand then decreased to a room temperature. Further, this heat treatmentmay be performed before formation of the oxide insulating film under areduced pressure. Under the reduced pressure, the heat treatment timecan be shortened. By the heat treatment, hydrogen is taken in the oxideinsulating layer from the oxide semiconductor layer.

By the formation of the drain region 414 b in part of the oxidesemiconductor layer, which overlaps with the drain electrode layer 415b, reliability of the thin film transistor can be improved.Specifically, by the formation of the drain region 414 b, a structure inwhich conductivity can be varied from the drain electrode layer 415 b tothe channel formation region 413 through the drain region 414 b can beobtained. Thus, because the drain region 414 b serves as a buffer, alocalized high electric field is not applied to the transistor even whena high electric field is applied between the gate electrode layer 411and the drain electrode layer 415 b, so that the transistor can haveincreased withstand voltage.

Further, the source region or the drain region in the oxidesemiconductor layer is formed in the entire thickness direction in thecase where the thickness of the oxide semiconductor layer is 15 nm orless. In the case where the thickness of the oxide semiconductor layeris 30 nm to 50 nm inclusive, in part of the oxide semiconductor layer,that is, in a region in the oxide semiconductor layer, which is incontact with the source electrode layer or the drain electrode layer,and the vicinity thereof, resistance is reduced and the source region orthe drain region is formed, while a region in the oxide semiconductorlayer, which is close to the gate insulating layer, can be made to bei-type.

A protective insulating layer may be additionally formed over the oxideinsulating layer 416. For example, a silicon nitride film is formed byRF sputtering. Since RF sputtering realizes high productivity, it ispreferably used as a film formation method of the protective insulatinglayer. The protective insulating layer 403 is formed using an inorganicinsulating film which does not contain impurities such as moisture, ahydrogen ion, and OH⁻ and blocks entry of these impurities from theoutside; for example, a silicon nitride film, an aluminum nitride film,a silicon nitride oxide film, an aluminum oxynitride film, or the likeis used. In Embodiment 2, as the protective insulating layer, aprotective insulating layer 403 is formed using a silicon nitride film(see FIG. 12D).

Modification Example

The above liquid crystal display device is an example of a liquidcrystal display device in Embodiment 2, and Embodiment 2 includes aliquid crystal display device having a difference with the above liquidcrystal display device.

For example, in the above liquid crystal display device, the pixel isformed using the circuit illustrated in FIG. 7B; however, the pixel canhave any of pixel structures illustrated in FIGS. 13A to 13D.

A circuit illustrated in FIG. 13A is different from that in FIG. 7B inthat the other terminal of the capacitor 78 and the other terminal ofthe liquid crystal element 79 are electrically connected to differentwirings. In the circuit in FIG. 7B, it becomes possible to control avoltage applied to the liquid crystal element 79 by controlling apotential of the wiring electrically connected to the other terminal ofthe capacitor 78.

A circuit illustrated in FIG. 13B is different from that in FIG. 7B inthat the capacitor 78 is not provided. The off-state current of theabove thin film transistor (see FIG. 12) is extremely low. That is, thevariation of the voltage applied to the liquid crystal element 79 can besuppressed even when the capacitor 78 is not provided. Accordingly, thepixel 76 can hold display even when the capacitor 78 is not provided.Note that in the structure, since leakage of charge through the liquidcrystal element 79 considerably affects the voltage applied to theliquid crystal element 79 itself, a liquid crystal material used for theliquid crystal element 79 is preferably a material with a high specificresistance. Specifically, the specific resistance of the liquid crystalmaterial is preferably 1×10¹¹Ω·cm or more, more preferably 1×10¹²Ω·cm ormore. In addition, in a pixel in FIG. 13B, improvement of the apertureratio, high-speed input of an image signal, or the like can be realized.

A circuit illustrated in FIG. 13C has a structure in which a transistor130 is added to the circuit in FIG. 13B. The structure can lead tofurther reduction of the variation of the voltage applied to the liquidcrystal element 79.

A circuit illustrated in FIG. 13D has a structure in which thetransistor 130 is added to the circuit in FIG. 7B. The structure canlead to further reduction in the variation of the voltage applied to theliquid crystal element 79.

Moreover, in the above liquid crystal display device, a thin filmtransistor called a channel etched transistor, which is one kind ofbottom gate structure. However, the structure of the thin filmtransistor is not limited to a particular structure. For example, thethin film transistor can have one kind of bottom gate structure called achannel stop type, a top gate structure, or the like. Further, the thinfilm transistor can have a structure in which gate electrode layers areprovided below and over the channel formation region.

Note that this embodiment or part of this embodiment can be freelycombined with the other embodiments or part of the other embodiments.

Embodiment 3

In Embodiment 3, an example of an active matrix liquid crystal displaydevice described in Embodiment 1 will be illustrated in more detail.Specifically, an example of inversion driving performed in the liquidcrystal display device will be described with reference to FIGS. 14A to14C, FIGS. 15A and 15B, FIGS. 16A to 16C, and FIG. 17. Note that here,as illustrated in FIG. 1A, image signals are input to a pixel group (thepixels 141, 142, 143, 144, and the like) included in the region 14 fourtimes per unit time, and image signals are input to a pixel group (thepixel 151, 152, 153, 154, and the like) included in the region 15 onetime per unit time. Further, each pixel has the circuit structureillustrated in FIG. 7B.

FIGS. 14A to 14C illustrate an example of polarities of an image signal(DATA(14)) input to a pixel included in the region 14 illustrated inFIG. 1A and an image signal (DATA(15)) input to a pixel included in theregion 15 illustrated in FIG. 1A. Note that in FIGS. 14A to 14C, thecase where an image signal input to one terminal of the liquid crystalelement 79 illustrated in FIG. 7B has a potential higher than commonpotential (Vcom) and the case where an image signal input to oneterminal of the liquid crystal element 79 illustrated in FIG. 7B has apotential lower than the common potential (Vcom) are expressed “P” and“N”, respectively. In addition, “T1” to “T8” have the same length andare successive periods.

As illustrated in FIGS. 14A to 14C, the number of “P”s and the number of“N”s are controlled to be the same in a certain period (here, “T1” to“T8”), so that deterioration of the liquid crystal element 79 can besuppressed. Further, when an image data is also input to the regionwhere the number of image signals input per unit time (here, “T1” to“T4” or “T5” to “T8”) is different (here, “T1” or “T5”), the polaritiesof image signals input to the regions is preferably the same. That is,when image signals are input to the entire pixel portion, the polaritiesof the image signals are preferably the same. Therefore, the imagesignal is not changed with crossing the common potential (Vcom) in theperiod (here, “T1” or “T5”). That is, an increase of power consumptionaccompanying with an input of the image signal can be suppressed to beas little as possible.

Further, when the inversion driving is performed, as illustrated inFIGS. 14A to 14C, the order of “P” and “N” can be designed arbitrarilyas long as the number of “P”s and the number of “N”s are the same in acertain period. For example, when the main purpose is reduction in powerconsumption, it is preferable that the polarity of an image signal beinverted as little as possible. Specifically, it is preferable to designthe order as illustrated in FIG. 14A. In contrast, when the main purposeis improvement in quality of a displayed image (or a moving image), itis preferable that the polarity of an image signal be inverted as muchas possible. Specifically, it is preferable to design as illustrated inFIG. 14B.

Furthermore, the inversion driving in which the polarity of image datais inverted every specific region of the pixel portion is preferablyperformed in addition to the above inversion driving (in a certainperiod, a plurality of image signals is input to a pixel, the pluralityof image signals includes an image signal with a potential higher than acommon potential (Vcom) and an image signal with a potential lower thana common potential (Vcom), and the number of the former and that of thelatter are the same). First, the case where inversion driving isperformed every column on a plurality of pixels arranged in matrix willbe described with reference to FIGS. 15A and 15B.

FIGS. 15A and 15B illustrate an example of the polarities of imagesignals input to the pixel 141 (DATA(141)) to the pixel 144 (DATA(144))and image signals input to the pixel 151 (DATA(151)) to the pixel 154(DATA(154)). As illustrated in FIGS. 15A and 15B, quality of a displayedimage (or a moving image) is improved by inversion of the polarity of animage signal input to an adjacent pixel.

Then, the case where inversion driving is performed on each of aplurality of pixels arranged in matrix in addition to the aboveinversion driving (in a certain period, a plurality of image signals isinput to a pixel, the plurality of image signals includes an imagesignal with a potential higher than a common potential (Vcom) and animage signal with a potential lower than a common potential (Vcom), andthe number of the former and that of the latter are the same) will bedescribed with reference to FIGS. 16A to 16C and FIG. 17.

FIG. 16A illustrates a specific structure of part of the pixel portion.Specifically, FIG. 16A illustrates nine pixels and wirings electricallyconnected to the pixels. A pixel 1611 is electrically connected to agate line 161 and a source line 164. A pixel 1612 is electricallyconnected to the gate line 161 and a source line 165. A pixel 1613 iselectrically connected to the gate line 161 and a source line 166. Apixel 1621 is electrically connected to a gate line 162 and the sourceline 165. A pixel 1622 is electrically connected to the gate line 162and the source line 166. A pixel 1623 is electrically connected to thegate line 162 and a source line 167. A pixel 1631 is electricallyconnected to a gate line 163 and the source line 164. A pixel 1632 iselectrically connected to the gate line 163 and the source line 165. Apixel 1633 is electrically connected to the gate line 163 and the sourceline 166.

Further, the polarities of image signals input to the source lines 164to 167 illustrated in FIG. 16A are alternately inverted. That is, when apixel group illustrated in FIG. 16A is a pixel group included in theregion 14 illustrated in FIG. 1A, image signals are input as illustratedin FIG. 16B; and when a pixel group illustrated in FIG. 16A is a pixelgroup included in the region 15 illustrated in FIG. 1A, image signalsare input as illustrated in FIG. 16C. Note that in FIGS. 16B and 16C,DATA(164) represents an image signal input to a pixel through the sourceline 164 and the same applies to DATA(165) to DATA(167).

In a pixel structure illustrated in FIG. 16A, an image signal is inputas illustrated in FIG. 16B or 16C, so that an image signal is input toeach pixel as illustrated in FIG. 17. That is, it is possible to performinversion driving on each pixel. The inversion driving can lead toimprovement of the quality of a displayed image (or a moving image).

Note that this embodiment or part of this embodiment can be freelycombined with the other embodiments or part of the other embodiments.

Embodiment 4

In Embodiment 4, examples of an electronic appliance on which a liquidcrystal display device obtained in Embodiments above is mounted aredescribed with reference to FIGS. 18A to 18F. Note that the liquidcrystal display device according to the above Embodiments is used for adisplay portion of an electronic device.

FIG. 18A illustrates a laptop computer, which includes a main body 2201,a housing 2202, a display portion 2203, a keyboard 2204, and the like.

FIG. 18B illustrates a portable information terminal device (PDA), whichincludes a main body 2211 provided with a display portion 2213, anexternal interface 2215, an operation button 2214, and the like. Astylus 2212 for operation is included as an accessory.

FIG. 18C illustrates an e-book reader 2220 as an example of anelectronic paper. The e-book reader 2220 includes two housings, ahousing 2221 and a housing 2223. The housings 2221 and 2223 are boundwith each other by an axis portion 2237, along which the e-book reader2220 can be opened and closed. With such a structure, the e-book reader2220 can be used as paper books.

A display portion 2225 is incorporated in the housing 2221, and adisplay portion 2227 is incorporated in the housing 2223. The displayportion 2225 and the display portion 2227 may display one image ordifferent images. In the structure where the display portions displaydifferent images from each other, for example, the right display portion(the display portion 2225 in FIG. 18C) can display text and the leftdisplay portion (the display portion 2227 in FIG. 18C) can displayimages.

Further, in FIG. 18C, the housing 2221 is provided with an operationportion and the like. For example, the housing 2221 is provided with apower supply 2231, an operation key 2233, a speaker 2235, and the like.With the operation key 2233, pages can be turned. Note that a keyboard,a pointing device, or the like may also be provided on the surface ofthe housing, on which the display portion is provided. Furthermore, anexternal connection terminal (an earphone terminal, a USB terminal, aterminal that can be connected to various cables such as an AC adapterand a USB cable, or the like), a recording medium insertion portion, andthe like may be provided on the back surface or the side surface of thehousing. Further, the e-book reader 2220 may have a function of anelectronic dictionary.

The e-book reader 2220 may be configured to transmit and receive datawirelessly. Through wireless communication, desired book data or thelike can be purchased and downloaded from an e-book reader server.

Note that electronic paper can be used for electronic appliances in allfields as long as they display data. For example, electronic paper canbe used for, instead of e-book reader, posters, advertisement invehicles such as trains, display in a variety of cards such as creditcards, and so on.

FIG. 18D illustrates a mobile phone, which includes two housings: ahousing 2240 and a housing 2241. The housing 2241 is provided with adisplay panel 2242, a speaker 2243, a microphone 2244, a pointing device2246, a camera lens 2247, an external connection terminal 2248, and thelike. The housing 2240 is provided with a solar cell 2249 charging ofthe mobile phone, an external memory slot 2250, and the like. An antennais incorporated in the housing 2241.

The display panel 2242 has a touch panel function. A plurality ofoperation keys 2245 which is displayed as images is illustrated bydashed lines in FIG. 18D. Note that the mobile phone includes a boostercircuit for increasing a voltage output from the solar cell 2249 to avoltage needed for each circuit. Further, in addition to the abovestructure, a contactless IC chip, a small memory device, or the like maybe incorporated.

The display orientation of the display panel 2242 changes as appropriatein accordance with the application mode. Further, the camera lens 2247is provided on the same surface as the display panel 2242, and thus, itcan be used as a video phone. The speaker 2243 and the microphone 2224can be used for videophone calls, recording, and playing sound, etc. aswell as voice calls. Moreover, the housings 2240 and 2241 in a statewhere they are developed as illustrated in FIG. 18D can be slid so thatone is lapped over the other; therefore, the size of the mobile phonecan be reduced, which makes the mobile phone suitable for being carried.

The external connection terminal 2248 can be connected to an AC adapteror a variety of cables such as a USB cable, which enables charging ofthe mobile phone and data communication between the mobile phone and thelike. Moreover, a larger amount of data can be saved and moved byinserting a recording medium to the external memory slot 2250. Further,in addition to the above functions, an infrared communication function,a television reception function, or the like may be provided.

FIG. 18E illustrates a digital camera, which includes a main body 2261,a display portion (A) 2267, an eyepiece 2263, an operation switch 2264,a display portion (B) 2265, a battery 2266, and the like.

FIG. 18F illustrates a television set 2270, which includes a displayportion 2273 incorporated in a housing 2271. The display portion 2273can display images. Here, the housing 2271 is supported by a stand 2275.

The television set 2270 can be operated by an operation switch of thehousing 2271 or a separate remote controller 2280. Channels and volumecan be controlled with an operation key 2279 of the remote controller2280 so that an image displayed in the display portion 2273 can becontrolled. Moreover, the remote controller 2280 may have a displayportion 2227 in which the information outgoing from the remotecontroller 2280 is displayed.

Note that the television set 2270 is preferably provided with areceiver, a modem, and the like. With the receiver, a general televisionbroadcast can be received. Furthermore, when the television set 2270 isconnected to a communication network by wired or wireless connectionthrough the modem, one-way (from a transmitter to a receiver) or two-way(between a transmitter and a receiver, between receivers, or the like)data communication can be performed.

This application is based on Japanese Patent Application serial no.2009-276269 filed with the Japan Patent Office on Dec. 4, 2009, theentire contents of which are hereby incorporated by reference.

1. A display device comprising: a processor configured to compare afirst image and a second image formed in accordance with image signalsinput from the outside and generates an image signal for forming a thirdimage for being interpolated between the first image and the secondimage; a gate driver and a source driver whose operations are controlledby an output signal of the processor; and a pixel portion where displayis performed by output signals of the gate driver and the source driver,wherein the pixel portion comprising a plurality of a thin filmtransistor using a oxide semiconductor film as a channel formationregion is divided into a plurality of regions and whether an imagesignal for forming the third image is input or not is selected dependingon a region of the plurality of regions.
 2. The display device accordingto the claim 1, wherein the gate driver comprises: a shift registerincluding a flip-flop; and an output control circuit to which an outputsignal of the flip-flop is input, wherein the output control circuitcomprises an AND gate with a first input terminal to which an outputsignal of the processor is input and a second input terminal to which anoutput signal of the flip-flop is input.
 3. The display device accordingto the claim 1, wherein the source driver comprises: a shift registerincluding a flip-flop; an output control circuit to which an outputsignal of the flip-flop is input; and a sampling circuit to which anoutput signal of the output control circuit is input, wherein the outputcontrol circuit comprises an AND gate with a first input terminal towhich an output signal of the processor is input and a second inputterminal to which an output signal of the flip-flop is input.
 4. Thedisplay device according to the claim 1, wherein carrier density of theoxide semiconductor film is less than 1×10¹²/cm³.
 5. The display deviceaccording to the claim 1, wherein hydrogen concentration of the oxidesemiconductor film is less than 1×10¹⁶/cm³.
 6. The display deviceaccording to the claim 1, wherein the display device is a liquid crystaldisplay device.
 7. A display device comprising: a processor configuredto compare a first image and a second image formed in accordance withimage signals input from the outside and generates image signals forforming a third image to an n-th image (n is a natural number of 4 ormore) which are to be interpolated between the first image and thesecond image; a gate driver and a source driver whose operations arecontrolled by an output signal of the processor; and a pixel portionwhere display is performed by output signals of the gate driver and thesource driver, wherein the pixel portion comprising a plurality of athin film transistor using a oxide semiconductor film as a channelformation region is divided into a plurality of regions and whether theimage signals for forming the third image to the n-th image are input ornot is selected depending on a region of the plurality of regions. 8.The display device according to the claim 7, wherein the gate drivercomprises: a shift register including a flip-flop; and an output controlcircuit to which an output signal of the flip-flop is input, wherein theoutput control circuit comprises an AND gate with a first input terminalto which an output signal of the processor is input and a second inputterminal to which an output signal of the flip-flop is input.
 9. Thedisplay device according to the claim 7, wherein the source drivercomprises: a shift register including a flip-flop; an output controlcircuit to which an output signal of the flip-flop is input; and asampling circuit to which an output signal of the output control circuitis input, wherein the output control circuit comprises an AND gate witha first input terminal to which an output signal of the processor isinput and a second input terminal to which an output signal of theflip-flop is input.
 10. The display device according to the claim 7,wherein carrier density of the oxide semiconductor film is less than1×10¹²/cm³.
 11. The display device according to the claim 7, whereinhydrogen concentration of the oxide semiconductor film is less than1×10¹⁶/cm³.
 12. The display device according to the claim 7, wherein thedisplay device is a liquid crystal display device.